WIRE BOND SHEAR TEST
standard by JEDEC Solid State Technology Association, 08/01/2009
RECOMMENDED ESD TARGET LEVELS FOR HBM QUALIFICATION
standard by JEDEC Solid State Technology Association, 07/01/2018
GDDR5 Measurement Procedures
standard by JEDEC Solid State Technology Association, 2014
ADDENDUM No. 2 to JESD35 – TEST CRITERIA FOR THE WAFER-LEVEL TESTING OF THIN DIELECTRICS
standard by JEDEC Solid State Technology Association, 02/01/1996
STANDARD DESCRIPTION OF 1.2 V CMOS LOGIC DEVICES (WIDE RANGE OPERATION)
standard by JEDEC Solid State Technology Association, 06/01/2001
DEFINITION OF CDCV857 PLL CLOCK DRIVER FOR REGISTERED DDR DIMM APPLICATIONS
standard by JEDEC Solid State Technology Association, 07/01/2000
EXTERNAL VISUAL
standard by JEDEC Solid State Technology Association, 10/01/2015
, Test Procedure for the Measurement of Terrestrial Cosmic Ray Induced Destructive Effects in Power Semiconductor Devices
standard by JEDEC Solid State Technology Association, 12/01/2015
DDR4 SDRAM Standard
standard by JEDEC Solid State Technology Association, 09/01/2012
STRESS-TEST-DRIVEN QUALIFICATION OF AND FAILURE MECHANISMS ASSOCIATED WITH ASSEMBLED SOLID STATE SURFACE-MOUNT COMPONENTS
standard by JEDEC Solid State Technology Association, 05/01/2005
HIGHLY ACCELERATED TEMPERATURE AND HUMIDITY STRESS TEST (HAST)
standard by JEDEC Solid State Technology Association, 11/01/2010
HERMETICITY
standard by JEDEC Solid State Technology Association, 07/01/2001