UNDERSTANDING ELECTRICAL OVERSTRESS – EOS
standard by JEDEC Solid State Technology Association, 09/01/2016

CHIP-PACKAGE INTERACTION UNDERSTANDING, IDENTIFICATION AND EVALUATION
standard by JEDEC Solid State Technology Association, 03/01/2018

CHIP-PACKAGE INTERACTION UNDERSTANDING, IDENTIFICATION AND EVALUATION
standard by JEDEC Solid State Technology Association, 03/01/2009

JOINT JEDEC/ECA STANDARD, DEFINING "LOW-HALOGEN" PASSIVES AND SOLID STATE DEVICES (Removal of BFR/CFR/PVC)
standard by JEDEC Solid State Technology Association, 05/01/2012

MEASUREMENT OF TRANSISTOR NOISE FIGURE AT MF, HF, AND VHF
standard by JEDEC Solid State Technology Association, 11/01/1981

TEMPERATURE, BIAS, AND OPERATING LIFE
standard by JEDEC Solid State Technology Association, 06/01/2005

POWER MOSFETS
standard by JEDEC Solid State Technology Association, 07/01/1985

GUIDELINE FOR CONSTANT TEMPERATURE AGING TO CHARACTERIZE ALUMINUM INTERCONNECT METALLIZATIONS FOR STRESS-INDUCED VOIDING
standard by JEDEC Solid State Technology Association, 12/01/2000

Embedded Multi-media card (e*MMC), Electrical Standard (5.01)
standard by JEDEC Solid State Technology Association, 07/01/2014

GDDR5 SGRAM
standard by JEDEC Solid State Technology Association, 09/01/2009

BALL GRID ARRAY PINOUT FOR 1-, 2-, AND 3-BIT LOGIC FUNCTIONS
standard by JEDEC Solid State Technology Association, 03/01/2004

INFORMATION REQUIREMENTS FOR THE QUALIFICATION OF SILICON DEVICES
standard by JEDEC Solid State Technology Association, 11/01/2017