Addendum No. 1 to JESD251, Optional x4 Quad I/O With Data Strobe
Amendment by JEDEC Solid State Technology Association, 10/01/2018

DEFINITION OF THE SSTUB32868 1.8 V CONFIGURABLE REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS
standard by JEDEC Solid State Technology Association, 10/01/2006

2.5 V BiCMOS LOGIC DEVICE FAMILY SPECIFICATION WITH 5 V TOLERANT INPUTS AND OUTPUTS
standard by JEDEC Solid State Technology Association, 06/01/1999

CERAMIC PACKAGE SPECIFICATION FOR MICROELECTRONIC PACKAGES
standard by JEDEC Solid State Technology Association, 08/01/1993

IPC/JEDEC-9702: MONOTONIC BEND CHARACTERIZATION OF BOARD-LEVEL INTERCONNECTS (IPC/JEDEC-9702)
standard by JEDEC Solid State Technology Association, 06/01/2004

PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK ANALYZER (VNA)
standard by JEDEC Solid State Technology Association, 10/01/2003

TEST METHOD FOR BEAM ACCELERATED SOFT ERROR RATE
standard by JEDEC Solid State Technology Association, 11/01/2007

PROCESS FAILURE MODE AND EFFECTS ANALYSIS (FMEA)
standard by JEDEC Solid State Technology Association, 05/01/2005

DOUBLE DATA RATE (DDR) SDRAM SPECIFICATION
standard by JEDEC Solid State Technology Association, 02/01/2008

ACCELERATED MOISTURE RESISTANCE – UNBIASED HAST
standard by JEDEC Solid State Technology Association, 07/01/2015

HIGHLY ACCELERATED TEMPERATURE AND HUMIDITY STRESS TEST (HAST)
standard by JEDEC Solid State Technology Association, 01/01/2009

RECOMMENDED ESD TARGET LEVELS FOR HBM/MM QUALIFICATION
standard by JEDEC Solid State Technology Association, 03/01/2012