DEFINITION OF THE SSTUB32868 1.8 V CONFIGURABLE REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS
standard by JEDEC Solid State Technology Association, 10/01/2006

2.5 V BiCMOS LOGIC DEVICE FAMILY SPECIFICATION WITH 5 V TOLERANT INPUTS AND OUTPUTS
standard by JEDEC Solid State Technology Association, 06/01/1999

CERAMIC PACKAGE SPECIFICATION FOR MICROELECTRONIC PACKAGES
standard by JEDEC Solid State Technology Association, 08/01/1993

IPC/JEDEC-9702: MONOTONIC BEND CHARACTERIZATION OF BOARD-LEVEL INTERCONNECTS (IPC/JEDEC-9702)
standard by JEDEC Solid State Technology Association, 06/01/2004

BALL GRID ARRAY PINOUTS STANDARDIZED FOR 16, 18, AND 20-BIT LOGIC FUNCTIONS USING A 54 BALL PACKAGE
standard by JEDEC Solid State Technology Association, 10/01/2001

DOUBLE DATA RATE (DDR) SDRAM SPECIFICATION
standard by JEDEC Solid State Technology Association, 02/01/2008

PROCESS FAILURE MODE AND EFFECTS ANALYSIS (FMEA)
standard by JEDEC Solid State Technology Association, 05/01/2005

ACCELERATED MOISTURE RESISTANCE – UNBIASED HAST
standard by JEDEC Solid State Technology Association, 07/01/2015

HIGHLY ACCELERATED TEMPERATURE AND HUMIDITY STRESS TEST (HAST)
standard by JEDEC Solid State Technology Association, 01/01/2009

RECOMMENDED ESD TARGET LEVELS FOR HBM/MM QUALIFICATION
standard by JEDEC Solid State Technology Association, 03/01/2012

CHARACTERIZATION AND MONITORING OF THERMAL STRESS TEST OVEN TEMPURATURES
standard by JEDEC Solid State Technology Association, 03/01/2014

TEMPERATURE CYCLING
standard by JEDEC Solid State Technology Association, 10/01/2014