TRANSISTOR, GALLIUM ARSENIDE POWER FET, GENERIC SPECIFICATION
standard by JEDEC Solid State Technology Association, 07/01/1992

STANDARD FOR DESCRIPTION OF 2.5 V CMOS LOGIC DEVICES WITH 3.6 V CMOS TOLERANT INPUTS AND OUTPUTS
standard by JEDEC Solid State Technology Association, 10/01/2000

SELECTION OF BURN-IN/LIFE TEST CONDITIONS AND CRITICAL PARAMETERS FOR QML MICROCIRCUITS
standard by JEDEC Solid State Technology Association, 09/01/2015

HSUL_12 LPDDR2 and LPDDR3 I/O with Optional ODT
standard by JEDEC Solid State Technology Association, 04/01/2014

HIGH TEMPERATURE STORAGE LIFE
standard by JEDEC Solid State Technology Association, 12/01/2010

STANDARD LOGNORMAL ANALYSIS OF UNCENSORED DATA, AND OF SINGLY RIGHT -CENSORED DATA UTILIZING THE PERSSON AND ROOTZEN METHOD
standard by JEDEC Solid State Technology Association, 10/01/1992

MARKING, SYMBOLS, AND LABELS OF LEADED AND LEAD-FREE TERMINAL FINISHED MATERIALS USED IN ELECTRONIC ASSEMBLY
standard by JEDEC Solid State Technology Association, 04/01/2016

0.6 V Low Voltage Swing Terminated Logic (LVSTL06)
standard by JEDEC Solid State Technology Association, 12/01/2016

CHARACTERIZATION AND MONITORING OF THERMAL STRESS TEST OVEN TEMPURATURES
standard by JEDEC Solid State Technology Association, 01/01/2008

APPLICATION SPECIFIC QUALIFICATION USING KNOWLEDGE BASED TEST METHODOLOGY
standard by JEDEC Solid State Technology Association, 07/01/2008

SOLID STATE DRIVE (SSD) REQUIREMENTS AND ENDURANCE TEST METHOD
standard by JEDEC Solid State Technology Association, 09/01/2010

DDR4 SDRAM Standard
standard by JEDEC Solid State Technology Association, 06/01/2017