Serial Interface for Data Converters
standard by JEDEC Solid State Technology Association, 12/01/2017

INTERFACE STANDARD FOR NOMINAL 3.0 V/3.3 V SUPPLY DIGITAL INTEGRATED CIRCUITS
standard by JEDEC Solid State Technology Association, 09/01/2007

ADDENDUM No. 4 to JESD8 – CENTER-TAP-TERMINATED (CTT) INTERFACE LOW-LEVEL, HIGH-SPEED INTERFACE STANDARD FOR DIGITAL INTEGRATED CIRCUITS
standard by JEDEC Solid State Technology Association, 11/01/1993

ADDENDUM No. 1 TO EIA-397
Amendment by JEDEC Solid State Technology Association, 07/01/1980

TEST METHODS FOR THE COLLECTOR-BASE TIME CONSTANT AND FOR THE RESISTIVE PART OF THE COMMON-EMITTER INPUT IMPEDANCE
standard by JEDEC Solid State Technology Association, 11/01/1963

NAND Flash Interface Interoperability
standard by JEDEC Solid State Technology Association, 07/01/2014

LOW TEMPERATURE STORAGE LIFE
standard by JEDEC Solid State Technology Association, 10/01/2015

ADDENDUM No. 5 to JESD24 – SINGLE PULSE UNCLAMPED INDUCTIVE SWITCHING (UIS) AVALANCHE TEST METHOD
Amendment by JEDEC Solid State Technology Association, 08/01/1990

STATISTICAL PROCESS CONTROL SYSTEMS
standard by JEDEC Solid State Technology Association, 04/01/2015

ADDENDUM No. 4 to JESD12 – METHOD OF SPECIFICATION OF PERFORMANCE PARAMETERS FOR CMOS SEMICUSTOM INTEGRATED CIRCUITS
Amendment by JEDEC Solid State Technology Association, 04/01/1987

STANDARD FOR DESCRIPTION OF FAST CMOS TTL COMPATIBLE LOGIC
standard by JEDEC Solid State Technology Association, 01/01/1993

DEFINITION OF THE SSTE32882 REGISTERING CLOCK DRIVER WITH PARITY AND QUAD CHIP SELECTS FOR DDR3/DDR3L/DDR3U RDIMM 1.5 V/1.35 V/1.25 V APPLICATIONS
standard by JEDEC Solid State Technology Association, 12/01/2010