PROCEDURE FOR WAFER-LEVEL-TESTING OF THIN DIELECTRICS
standard by JEDEC Solid State Technology Association, 03/01/2010

Handling, Packing, Shipping and Use of Moisture, Reflow, and Process Sensitive Devices
standard by JEDEC Solid State Technology Association, 04/01/2018

ESDA/JEDEC Joint Standard for Electrostatic Discharge Sensitivity Testing – Human Body Modal (HBM) – Component Level
standard by JEDEC Solid State Technology Association, 05/12/2017

Embedded Multi-media card (e*MMC), Electrical Standard 5.0
standard by JEDEC Solid State Technology Association, 09/01/2013

PSO-N/PQFN PINOUTS STANDARDIZED FOR 14-, 16-, 20-, AND 24-LEAD LOGIC FUNCTIONS
standard by JEDEC Solid State Technology Association, 03/01/2006

SYMBOL AND LABEL FOR ELECTROSTATIC SENSITIVE DEVICES
standard by JEDEC Solid State Technology Association,

ADDENDUM No. 9 to JESD24 – SHORT CIRCUIT WITHSTAND TIME TEST METHOD
Amendment by JEDEC Solid State Technology Association, 08/01/1992

ADDENDUM No. 6 to JESD8 – HIGH SPEED TRANSCEIVER LOGIC (HSTL)- A 1.5 V OUTPUT BUFFER SUPPLY VOLTAGE BASED INTERFACE STANDARD FOR DIGITAL INTEGRATED CIRCUITS
standard by JEDEC Solid State Technology Association, 08/01/1995

METHODS OF MEASUREMENT FOR SEMICONDUCTOR LOGIC GATING MICROCIRCUITS
standard by JEDEC Solid State Technology Association, 01/01/1970

Byte Addressable Energy Backed Interface
standard by JEDEC Solid State Technology Association, 09/01/2017

DICTIONARY OF TERMS FOR SOLID STATE TECHNOLOGY, FOURTH EDITION
standard by JEDEC Solid State Technology Association, 07/01/2007

ADDENDUM No. 5 to JESD12 – DESIGN FOR TESTABILITY GUIDELINES
Amendment by JEDEC Solid State Technology Association, 08/01/1988