RELIABILITY QUALIFICATION OF SEMICONDUCTOR DEVICES BASED ON PHYSICS OF FAILURE RISK AND OPPORTUNITY ASSESSMENT
standard by JEDEC Solid State Technology Association, 01/01/2014

.05 Low Voltage Swing Terminated Logic (LVSTL05)
standard by JEDEC Solid State Technology Association, 06/01/2019

CONSTANT-TEMPERATURE AGING METHOD TO CHARACTERIZE COPPER INTERCONNECT METALLIZATIONS FOR STRESS-INDUCED VOIDING
standard by JEDEC Solid State Technology Association, 08/01/2017

DIGITAL BIPOLAR LOGIC PINOUTS FOR CHIP CARRIERS
standard by JEDEC Solid State Technology Association, 12/01/1982

QUALITY SYSTEM ASSESSMENT
standard by JEDEC Solid State Technology Association, 10/01/2013

ELECTRICALLY ERASABLE PROGRAMMABLE ROM (EEPROM) PROGRAM/ERASE ENDURANCE AND DATA RETENTION TEST
standard by JEDEC Solid State Technology Association, 03/01/2009

STANDARD FOR DESCRIPTION OF 3.3 V NFET BUS SWITCH DEVICES WITH INTEGRATED CHARGE PUMPS
standard by JEDEC Solid State Technology Association, 08/01/2001

SERIAL FLASH RESET SIGNALING PROTOCOL
standard by JEDEC Solid State Technology Association, 10/01/2018

1.0 V +/- 0.1 V (NORMAL RANGE) AND 0.7 V – 1.1 V (WIDE RANGE) POWER SUPPLY VOLTAGE AND INTERFACE STANDARD FOR NONTERMINATED DIGITAL INTEGRATED CIRCUITS
standard by JEDEC Solid State Technology Association, 09/01/2007

A PROCEDURE FOR EXECUTING SWEAT
standard by JEDEC Solid State Technology Association, 08/01/2003

SEMICONDUCTOR WAFER AND DIE BACKSIDE EXTERNAL VISUAL INSPECTION
standard by JEDEC Solid State Technology Association, 03/01/2011

Thermal Test Chip Guideline (Wire Bond Type Chip)
standard by JEDEC Solid State Technology Association, 06/01/2019