PACKAGE WARPAGE MEASUREMENT OF SURFACE-MOUNT INTEGRATED CIRCUITS AT ELEVATED TEMPERATURE
standard by JEDEC Solid State Technology Association, 10/01/2009

FBDIMM Architecture and Protocol
standard by JEDEC Solid State Technology Association, 01/01/2007

SIGNATURE ANALYSIS
standard by JEDEC Solid State Technology Association, 07/01/1999

ADDENDUM No. 8 to JESD8 – STUB SERIES TERMINATED LOGIC FOR 3.3 VOLTS (SSTL_3) A 3.3 V VOLTAGE BASED INTERFACE STANDARD FOR DIGITAL INTEGRATED CIRCUITS
standard by JEDEC Solid State Technology Association, 08/01/1996

Embedded Multi-media card (e*MMC), Electrical Standard (4.5 Device)
standard by JEDEC Solid State Technology Association, 06/01/2011

A PROCEDURE FOR MEASURING P-CHANNEL MOSFET HOT-CARRIER-INDUCED DEGRADATION AT MAXIMUM GATE CURRENT UNDER DC STRESS
standard by JEDEC Solid State Technology Association, 09/01/2004

Component Quality Problem Analysis and Corrective Action Requirements (Including Administrative Quality Problems)
standard by JEDEC Solid State Technology Association, 07/01/2018

METAL PACKAGE SPECIFICATION FOR MICROELECTRONIC PACKAGES AND COVERS
standard by JEDEC Solid State Technology Association, 04/01/1987

GUIDELINE FOR RESIDUAL GAS ANALYSIS (RGA) FOR MICROELECTRONIC PACKAGES
standard by JEDEC Solid State Technology Association, 11/01/2011

JEDEC Dictionary of Terms for Solid-State Technology, Sixth Edition
standard by JEDEC Solid State Technology Association, 06/01/2013

GUIDELINE FOR RESIDUAL GAS ANALYSIS (RGA) FOR MICROELECTRONIC PACKAGES
standard by JEDEC Solid State Technology Association, 07/01/2002

ELECTRICALLY ERASABLE PROGRAMMABLE ROM (EEPROM) PROGRAM/ERASE ENDURANCE AND DATA RETENTION TEST
standard by JEDEC Solid State Technology Association, 11/01/2018