ADDENDUM No. 2 to JESD8 – STANDARD FOR OPERATING VOLTAGES AND INTERFACE LEVELS FOR LOW VOLTAGE EMITTER-COUPLED LOGIC (ECL) INTEGRATED CIRCUITS
standard by JEDEC Solid State Technology Association, 03/01/1993

DISCONTINUING USE OF THE MACHINE MODEL FOR DEVICE ESD QUALIFICATION
standard by JEDEC Solid State Technology Association, 07/01/2014

Universal Flash Storage (UFS)
standard by JEDEC Solid State Technology Association, 06/01/2012

RADIO FRONT END – BASEBAND DIGITAL PARALLEL (RBDP) INTERFACE
standard by JEDEC Solid State Technology Association, 03/01/2007

MARK LEGIBILITY
standard by JEDEC Solid State Technology Association, 03/01/2008

Power Cycling
standard by JEDEC Solid State Technology Association, 06/01/2016

PREFERRED LEAD CONFIGURATION FOR FIELD-EFFECT TRANSISTORS
standard by JEDEC Solid State Technology Association, 11/01/1973

A PROCEDURE FOR MEASURING P-CHANNEL MOSFET NEGATIVE BIAS TEMPERATURE INSTABILITIES
standard by JEDEC Solid State Technology Association, 11/01/2004

Addendum No. 2 to JESD79-3 – 1.35 V DDR3L-800, DDR3L-1066, DDR3L-1333, and DDR3L-1600
Amendment by JEDEC Solid State Technology Association, 10/01/2011

DDR2 SPD INTERPRETATION OF TEMPERATURE RANGE AND (SELF-) REFRESH OPERATION
standard by JEDEC Solid State Technology Association, 06/01/2006

EARLY LIFE FAILURE RATE CALCULATION PROCEDURE FOR SEMICONDUCTOR COMPONENTS
standard by JEDEC Solid State Technology Association, 02/01/2007

Byte Addressable Energy Backed Interface
standard by JEDEC Solid State Technology Association, 07/01/2017