A PROCEDURE FOR MEASURING P-CHANNEL MOSFET NEGATIVE BIAS TEMPERATURE INSTABILITIES
standard by JEDEC Solid State Technology Association, 11/01/2004
Addendum No. 2 to JESD79-3 – 1.35 V DDR3L-800, DDR3L-1066, DDR3L-1333, and DDR3L-1600
Amendment by JEDEC Solid State Technology Association, 10/01/2011
DDR2 SPD INTERPRETATION OF TEMPERATURE RANGE AND (SELF-) REFRESH OPERATION
standard by JEDEC Solid State Technology Association, 06/01/2006
EARLY LIFE FAILURE RATE CALCULATION PROCEDURE FOR SEMICONDUCTOR COMPONENTS
standard by JEDEC Solid State Technology Association, 02/01/2007
Byte Addressable Energy Backed Interface
standard by JEDEC Solid State Technology Association, 07/01/2017
TEST METHOD FOR REAL-TIME SOFT ERROR RATE
standard by JEDEC Solid State Technology Association, 10/01/2007
POD18 – 1.8 V Pseudo Open Drain I/O
standard by JEDEC Solid State Technology Association, 12/01/2006
DISCONTINUING USE OF THE MACHINE MODEL FOR DEVICE ESD QUALIFICATION
standard by JEDEC Solid State Technology Association, 07/01/2015
COUNTERFEIT ELECTRONIC PARTS: NON-PROLIFERATION FOR MANUFACTURERS
standard by JEDEC Solid State Technology Association, 03/01/2016
ADDENDUM No. 11 to JESD24 – POWER MOSFET EQUIVALENT SERIES GATE RESISTANCE TEST METHOD
Amendment by JEDEC Solid State Technology Association, 08/01/1996
TERMS, DEFINITIONS, AND LETTER SYMBOLS FOR MICROELECTRONIC DEVICES
standard by JEDEC Solid State Technology Association, 05/01/2007
DESCRIPTION OF 5 V BUS SWITCH WITH TTL-COMPATIBLE CONTROL INPUTS
standard by JEDEC Solid State Technology Association, 06/01/1999