DEFINITION OF THE SSTV32852 2.5 V 24-BIT TO 48-BIT SSTL_2 REGISTERED BUFFER FOR 1U STACKED DDR DIMM APPLICATIONS
standard by JEDEC Solid State Technology Association, 11/01/2004
HIgh Bandwidth Memory DRAM (HBM1, HBM2)
standard by JEDEC Solid State Technology Association, 11/01/2018
DDR4 REGISTER CLOCK DRIVER (DDR4RCD01)
standard by JEDEC Solid State Technology Association, 08/01/2016
FOUNDRY PROCESS QUALIFICATION GUIDELINES (Wafer Fabrication Manufacturing Sites)
standard by JEDEC Solid State Technology Association, 02/01/2014
TEST PROCEDURE FOR THE MANAGEMENT OF SINGLE-EVENT EFFECTS IN SEMICONDUCTOR DEVICES FROM HEAVY ION IRRADIATION
standard by JEDEC Solid State Technology Association, 12/01/1996
MEASUREMENT OF TEMPERATURE COEFFICIENT OF VOLTAGE REGULATOR DIODES
standard by JEDEC Solid State Technology Association, 02/01/1982
POD12-1.2 V Pseudo Open Drain Interface
standard by JEDEC Solid State Technology Association, 08/01/2011
STANDARD FOR DESCRIPTION OF 2.5 V CMOS LOGIC DEVICES
standard by JEDEC Solid State Technology Association, 11/01/1999
SOLDER BALL PULL
standard by JEDEC Solid State Technology Association, 05/01/2007
SUBASSEMBLY MECHANICAL SHOCK
standard by JEDEC Solid State Technology Association, 11/01/2004
SPECIAL REQUIREMENTS FOR MAVERICK PRODUCT ELIMINATION AND OUTLIER MANAGEMENT
standard by JEDEC Solid State Technology Association, 01/01/2018
Low Power Double Data Rate 4 (LPDDR4)
standard by JEDEC Solid State Technology Association, 2015