BALL GRID ARRAY PINOUTS STANDARDIZED FOR 8-BIT LOGIC FUNCTIONS
standard by JEDEC Solid State Technology Association, 07/01/2001

STANDARD DATA TRANSFER FORMAT BETWEEN DATA PREPARATION SYSTEM AND PROGRAMMABLE LOGIC DEVICE PROGRAMMER
standard by JEDEC Solid State Technology Association, 06/01/1994

Universal Flash Storage Host Controller Interface (UFSHCI), Unified Memory Extension
standard by JEDEC Solid State Technology Association, 03/01/2016

SOLDER BALL SHEAR
standard by JEDEC Solid State Technology Association, 10/01/2006

THERMAL SHOCK
standard by JEDEC Solid State Technology Association, 06/01/2004

DEFINITION OF the SSTUB32866 1.8 V CONFIGURABLE REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS
standard by JEDEC Solid State Technology Association, 05/01/2007

1.2 V +/- 0.1 V (NORMAL RANGE) AND 0.8 – 1.3 V (WIDE RANGE) POWER SUPPLY VOLTAGE AND INTERFACE STANDARD FOR NONTERMINATED DIGITAL INTEGRATED CIRCUITS
standard by JEDEC Solid State Technology Association, 09/01/2007

BOARD LEVEL DROP TEST METHOD OF COMPONENTS FOR HANDHELD ELECTRONIC PRODUCTS
standard by JEDEC Solid State Technology Association, 11/01/2016

MEASUREMENT AND REPORTING OF ALPHA PARTICLE AND TERRESTRIAL COSMIC RAY INDUCED SOFT ERRORS IN SEMICONDUCTOR DEVICES
standard by JEDEC Solid State Technology Association, 10/01/2006

ENVIRONMENTAL ACCEPTANCE REQUIREMENTS FOR TIN WHISKER SUSCEPTIBILITY OF TIN AND TIN ALLOY SURFACE FINISHED
standard by JEDEC Solid State Technology Association, 08/01/2008

BALL GRID ARRAY PINOUTS STANDARDIZED FOR 32-BIT LOGIC FUNCTIONS
standard by JEDEC Solid State Technology Association, 11/01/1999

Graphics Double Data Rate (GDDR5) SGRAM Standard
standard by JEDEC Solid State Technology Association, 02/01/2016