ADDENDUM No. 11A.01 to JESD8 – 1.5 V +/- 0.1 V (NORMAL RANGE) AND 0.9 – 1.6 V (WIDE RANGE) POWER SUPPLY VOLTAGE AND INTERFACE STANDARD FOR NONTERMINATED DIGITAL INTEGRATED CIRCUITS
standard by JEDEC Solid State Technology Association, 09/01/2007

WIRE BOND SHEAR TEST
standard by JEDEC Solid State Technology Association, 04/01/2017

FBDIMM SPECIFICATION: HIGH SPEED DIFFERENTIAL PTP LINK AT 1.5 V
standard by JEDEC Solid State Technology Association, 03/01/2008

STANDARD TEST METHOD UTILIZING X-RAY FLUORESCENCE (XRF) FOR ANALYZING COMPONENT FINISHES AND SOLDER ALLOYS TO DETERMINE TIN (Sn) – LEAD (Pb) CONTENT
standard by JEDEC Solid State Technology Association, 03/01/2010

INTEGRATED CIRCUITS THERMAL TEST METHOD ENVIRONMENTAL CONDITIONS – NATURAL CONVECTION (STILL AIR)
standard by JEDEC Solid State Technology Association, 01/01/2007

STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS
standard by JEDEC Solid State Technology Association, 04/01/2011

BOARD LEVEL CYCLIC BEND TEST METHOD FOR INTERCONNECT RELIABILITY CHARACTERIZATION OF SMT ICS FOR HANDHELD ELECTRONIC PRODUCTS
standard by JEDEC Solid State Technology Association, 08/01/2018

STANDARD DESCRIPTION OF 1.2 V CMOS LOGIC DEVICES (NORMAL RANGE OPERATION)
standard by JEDEC Solid State Technology Association, 06/01/2001

TEST BOARDS FOR THROUGH-HOLE AREA ARRAY LEADED PACKAGE THERMAL MEASUREMENT
standard by JEDEC Solid State Technology Association, 06/01/2001

STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS
standard by JEDEC Solid State Technology Association, 04/01/2010

PRECONDITIONING OF PLASTIC SURFACE MOUNT DEVICES PRIOR TO RELIABILITY TESTING
standard by JEDEC Solid State Technology Association, 10/01/2015

Serial Interface for Data Converters
standard by JEDEC Solid State Technology Association, 01/01/2012