Low Power Double Data Rate 5 (LPDDR5)
standard by JEDEC Solid State Technology Association, 02/01/2019
WIRE BOND SHEAR TEST
standard by JEDEC Solid State Technology Association, 04/01/2017
IC LATCH-UP TEST
standard by JEDEC Solid State Technology Association, 04/01/2016
ELECTROSTATIC DISCHARGE (ESD) SENSITIVITY TESTING MACHINE MODEL (MM)
standard by JEDEC Solid State Technology Association, 03/01/2010
LEADLESS CHIP CARRIER PINOUTS STANDARDIZED FOR LINEARS
standard by JEDEC Solid State Technology Association, 04/01/1982
TEST BOARDS FOR AREA ARRAY SURFACE MOUNT PACKAGE THERMAL MEASUREMENTS
standard by JEDEC Solid State Technology Association, 07/01/2000
THERMAL IMPEDANCE MEASUREMENT FOR INSULATED GATE BIPOLAR TRANSISTORS – (Delta VCE(on) Method)
Amendment by JEDEC Solid State Technology Association, 06/01/2004
DEFINITION OF 'CU878 PLL CLOCK DRIVER FOR REGISTERED DDR2 DIMM APPLICATIONS
standard by JEDEC Solid State Technology Association, 09/01/2004
Graphics Double Data Rate (GDDR6) SGRAM Standard
standard by JEDEC Solid State Technology Association, 11/01/2018
Lognormal Analysis of Uncensored Data, and of Singly Right-Censored Data Utilizing the Persson and Rootzen Method
standard by JEDEC Solid State Technology Association, 08/01/2017
THERMAL TEST BOARD STANDARDS TO ACCOMMODATE MULTI-CHIP PACKAGES
standard by JEDEC Solid State Technology Association, 12/01/2010
RESISTANCE TO SOLDER SHOCK FOR THROUGH-HOLE MOUNTED DEVICES
standard by JEDEC Solid State Technology Association, 11/01/2016