POD135 – 1.35 V PSEUDO OPEN DRAIN I/O
standard by JEDEC Solid State Technology Association, 09/01/2013

DESIGNATION SYSTEM FOR SEMICONDUCTOR DEVICES
standard by JEDEC Solid State Technology Association, 02/01/1982

COMPONENT QUALITY PROBLEM ANALYSIS AND CORRECTIVE ACTION REQUIREMENTS (INCLUDING ADMINISTRATIVE QUALITY PROBLEMS)
standard by JEDEC Solid State Technology Association, 12/01/1999

STANDARD FOR SELENIUM SURGE SUPPRESSORS
standard by JEDEC Solid State Technology Association, 11/01/1973

ASSESSMENT OF AVERAGE OUTGOING QUALITY LEVELS IN PARTS PER MILLION (PPM)
standard by JEDEC Solid State Technology Association, 04/01/1995

EXPANDED SERIAL PERIPHERAL INTERFACE (xSPI) FOR NON VOLATILE MEMORY DEVICES, VERSION 1.0
standard by JEDEC Solid State Technology Association, 08/01/2018

SOLID STATE DRIVE (SSD) REQUIREMENTS AND ENDURANCE TEST METHOD
standard by JEDEC Solid State Technology Association, 03/01/2016

UNIFIED WIDE POWER SUPPLY VOLTAGE RANGE CMOS DC INTERFACE STANDARD FOR NON-TERMINATED DIGITAL INTEGRATED CIRCUITS
standard by JEDEC Solid State Technology Association, 10/01/2009

RELIABILITY QUALIFICATION OF SEMICONDUCTOR DEVICES BASED ON PHYSICS OF FAILURE RISK AND OPPORTUNITY ASSESSMENT
standard by JEDEC Solid State Technology Association, 12/01/2008

SOLID STATE RELIABILITY ASSESSMENT QUALIFICATION METHODOLOGIES
standard by JEDEC Solid State Technology Association, 06/01/2008

INFORMATION REQUIREMENTS FOR THE QUALIFICATION OF SILICON DEVICES
standard by JEDEC Solid State Technology Association, 10/01/2007

ADDENDUM No. 9B to JESD8 – STUB SERIES TERMINATED LOGIC FOR 2.5 VOLTS (SSTL_2): Includes Errata and Corrected Page 7 as of October 18, 2002
standard by JEDEC Solid State Technology Association, 05/01/2002