INFORMATION REQUIREMENTS FOR THE QUALIFICATION OF SILICON DEVICES
standard by JEDEC Solid State Technology Association, 10/01/2007

ADDENDUM No. 9B to JESD8 – STUB SERIES TERMINATED LOGIC FOR 2.5 VOLTS (SSTL_2): Includes Errata and Corrected Page 7 as of October 18, 2002
standard by JEDEC Solid State Technology Association, 05/01/2002

PROCESS CHARACTERIZATION GUIDELINE
standard by JEDEC Solid State Technology Association, 08/01/2018

POD135 – 1.35 V PSEUDO OPEN DRAIN I/O
standard by JEDEC Solid State Technology Association, 07/01/2010

Inspection Criteria for Microelectronic Packages and Covers
standard by JEDEC Solid State Technology Association, 05/01/2017

WIRE BOND SHEAR TEST
standard by JEDEC Solid State Technology Association, 08/01/2009

RECOMMENDED ESD TARGET LEVELS FOR HBM QUALIFICATION
standard by JEDEC Solid State Technology Association, 07/01/2018

GDDR5 Measurement Procedures
standard by JEDEC Solid State Technology Association, 2014

ADDENDUM No. 2 to JESD35 – TEST CRITERIA FOR THE WAFER-LEVEL TESTING OF THIN DIELECTRICS
standard by JEDEC Solid State Technology Association, 02/01/1996

STANDARD DESCRIPTION OF 1.2 V CMOS LOGIC DEVICES (WIDE RANGE OPERATION)
standard by JEDEC Solid State Technology Association, 06/01/2001

DEFINITION OF CDCV857 PLL CLOCK DRIVER FOR REGISTERED DDR DIMM APPLICATIONS
standard by JEDEC Solid State Technology Association, 07/01/2000

EXTERNAL VISUAL
standard by JEDEC Solid State Technology Association, 10/01/2015