JEDEC JESD51-4
September 11, 2020
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This guideline describes design requirements for wire bond type semiconductor chips to be used for thermal resistance listing of IC packages. This document provides specific guidelines for chip design but allows flexibility in the materials and layout requirements.
Product Details
- Published:
- 02/01/1997
- Number of Pages:
- 15
- File Size:
- 1 file , 310 KB